Home Documents Publications
Publications

Selected publications (papers, posters, presentations) from the COMPLEX project.

DocumentsDate added

Order by : Name | Date | Hits [ Descendent ]

Abstract + Poster presentation at DEPCP workshop, co-located with DATE'2011.
Authors: Philipp A. Hartmann, Philipp Ittershagen, Kim Grüttner, Frank Oppenheimer, Achim Rettberg

Abstract + Poster presentation at DEPCP workshop, co-located with DATE'2011.
Authors: Fabien Colas-Bigey (Thales), Sara Boccio (ST-I), Chantal Ykman-Couvreur (IMEC), Gianluca Palermo (PoliMi), Philipp A. Hartmann (OFFIS)

Presentation given at DATE'2011 Exhibition Theatre session.
Franco Fummi, EDALab.

Keynote talk, given at ISCUG'2013
Philipp A. Hartmann – OFFIS

Abstract:

SystemC and TLM-2.0 based ESL methodologies are widely used for early application, platform, and performance analysis already. But the consideration of an embedded device's power consumption and its management is increasingly important nowadays, not only for mobile devices. Currently, it is not equally easily possible to integrate such extra-functional information at electronic system-level.

In this talk, the design challenges of today's heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators are discussed. Existing and new approaches for system-level timing and power estimation techniques, as well as their efficient integration into SystemC/TLM virtual prototypes are presented. To enable interoperability beyond timing and functionality, the need for future standardization efforts in the area of extra-functional properties is motivated.

Presentation given at DATE'2011 Exhibition Theatre session.
Emmanuel Vaumorin - Magillem.

An MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models

Presentation given at CODES+ISSS'2012.
Eugenio Villar (University of Cantabria, Spain)

Abstract: This talk presents the COMPLEX UML/MARTE modeling methodology and its related framework for automatic generation of executable performance models. The modeling methodology supports Model Driven Development (MDD), required by industrial flows, and a novel set of modeling features specifically suited for Design Space Exploration (DSE), a crucial design activity. The COMPLEX framework presents other main advantages for DSE. The COMPLEX tooling enables the automatic generation of an executable and configurable model for fast performance analysis without requiring engineering effort. The COMPLEX tooling automates the production of an easily portable text based representation of the UML/MARTE model. This text-based representation is read by the underlying simulation infrastructure, which automatically builds a fast performance model supporting the evaluation of different configurations of the system. A main aspect of the performance analysis framework is that it supports a system-level text-based front-end, which it is produced from the COMPLEX UML/MARTE model, and which avoids the development of SW implementations, HW refinements, or the implementation of HW/SW interfaces. Moreover, neither code regeneration, nor recompilation is required for all the DSE iterations, and thus, the time of the exploration is mostly due to model simulation.

Energy and timing analysis and optimization of embedded applications

Presentation given at CODES+ISSS'2012.
William Fornaciari, Carlo Brandolese (Politecnico di Milano, Italy)

Abstract: This talk presents a methodology and a toolchain to perform estimation and optimization of the energy consumption associated to software execution on tiny embedded systems. The estimation phase is based on an ISA-level characterization of the target processor, while the optimization phase is made combining the estimation process with design space exploration in order to exploit fine-grained dynamic voltage and frequency scaling. The proposed approach operates at compile-time, with the granularity of single C functions and almost automatically augments the source code.

From RTL IP to functional system-level models with extra-functional properties

Presentation given at CODES+ISSS'2012.
Daniel Lorenz (OFFIS, Germany)

Abstract: The talks presents a novel abstraction methodology for generating time- and power-annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration. With the proposed approach, IP models can be natively integrated into SystemC TLM-2.0 platforms and executed 10-1000 times faster compared to state-of-the-art RTL simulators. The abstraction methodology guarantees preservation of the behaviour and timing of the RTL models. Target technology dependent power properties of IP components are represented as power state-machines and integrated into the abstracted TLM models. The experimental results show a relative error less than 10% of the abstracted model's power consumption compared to state-of-the-art RTL power simulators. The evaluation has been performed on RTL IP components with different characteristics and demonstrates the effectiveness of the presented abstraction methodology.

 

Network-aware Design-Space Exploration of a Power-Efficient Embedded Application

Presentation given at CODES+ISSS'2012.
Parinaz Sayyah (Politecnico di Torino, Italy)

The talk presents the design and multi-parameter optimization of a networked embedded application for the health-care domain. Several hardware, software, and application parameters, such as clock frequency, sensor sampling rate, data packet rate, are tuned at design- and run-time according to application specifications and operating conditions to optimize hardware requirements, packet loss, power consumption.  Experimental results show that further power efficiency can be achieved by considering also communication aspects during design space exploration.

 

Run-time resource management based on design space exploration

Presentation given at CODES+ISSS'2012.
Chantal Couvreur (IMEC, Belgium)

Abstract: A main challenge in today's embedded system design is to find the perfect balance between performance and power consumption.  This paper presents a run-time resource management framework for embedded heterogeneous multi-core platforms. It allows dynamic adaptation to changing application context and transparent optimization of the platform resource usage following a distributed and hierarchical approach. A Global Resource Manager (GRM) is running in parallel with the central manager of the application on the host processor of the platform. Each IP core of the platform can execute its own Local Resource Manager (LRM), and the GRM conforms to practices of each LRM. The operating points managed by the GRM are identified in a design-space exploration phase as a set of Pareto-optimal configurations of the application and their impacts with regards to the quality of experience, performance and energy consumption. The GRM has already been integrated in a POSIX version of an audio-driven video surveillance application in order to maximize its QoE parameters with respect to the battery duration and the energy budget of the platform, used to analyze the GRM efficiency.

 

Introduction to special session at CODES+ISSS'2012.
Kim Grüttner (OFFIS, Germany)

Abstract + Poster presentation at uPM2SoC workshop, co-located with DATE'2011.
Authors: Kim Grüttner, Kai Hylla, Sven Rosinger, Philipp A. Hartmann, Wolfgang Nebel

Presentation given at  at workshop Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow (QVVP’12), DATE'2012, Dresden, Germany
Philipp A. Hartmann, OFFIS

Tutorial slides given during a master course at Universidad de los Andes, Bogotá , Columbia,
by Fernando Herrera, UC.

Tutorial presented at ISCUG'2013
Philipp A. Hartmann – OFFIS


Abstract:

Integrating third-party TLM-2.0 components into custom system models frequently requires the definition of wrappers to adapt the particular behaviour and analysis/tracing capabilities of such a component to the concrete needs of the overall platform. In this tutorial, a simple yet powerful mechanism for introspection and augmentation is presented, greatly reducing the amount of required boiler-plate code in such cases. Custom convenience sockets for transaction introspection and forwarding are introduced and required implementation techniques are discussed. In the second part, this augmentation mechanism is used to externally add power information in terms of a state-machine based abstraction to a pre-existing TLM-2.0 system.

Presentation at ESCUG'28
September 24th, 2013 – Paris, France
Philipp A. Hartmann, OFFIS

Abstract

SystemC and TLM-2.0 based ESL methodologies are widely used for early application, platform, and performance analysis already. But the consideration of an embedded device's power consumption and its management is increasingly important nowadays, not only for mobile devices. Currently, it is not equally easily possible to integrate and analyse such extra-functional information at electronic system-level.

In this talk, existing approaches for system-level timing and power estimation techniques, as well as their efficient integration into SystemC/TLM virtual prototypes are presented. As an enabling technology for the analysis of extra-functional system properties, an advanced tracing infrastructure especially addressing temporally decoupled virtual prototype simulations constitutes the main part of the presentation. Finally, to enable interoperability beyond timing and functionality, the need for future standardization efforts in the area of extra-functional properties is briefly outlined.

Tutorial, given at PATMOS'2011.
Héctor Posadas & Eugenio Villar, University of Cantabria

Slides of presentation at ESCUG'24 (co-located with FDL'2011)
Authors: Philipp A. Hartmann, Maher A. Fakih, Kim Grüttner, OFFIS

Integrating existing third-party TLM-2.0 components into custom system models frequently require the definition of wrappers to adapt the particular behaviour (or even analysis/tracing capabilities) of such a component to the concrete needs of the overall platform.

In this talk, a simple yet powerful framework based on augmentable convenience sockets is presented, greatly reducing the amount of required boiler-plate code in these cases. Transactions are automatically forwarded from/to their wrapped sockets, but can be analysed and even modified easily along the way. The benefits of the approach are demonstrated by externally adding dynamic power- management capabilities to a pre-existing TLM-2.0 system.

file icon QVVP'12 Workshop Digesthot!Tooltip 03/19/2012 Hits: 1339

Collection of extended abstracts and posters of the "Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow" (QVVP’12) Workshop at DATE'12, 16.03.2012

Nowadays, the deployment of Virtual Platform models is an industry-proven technique in a wide variety of design tasks from pre-silicon software development to performance analysis and exploration. With the increasing complexity, both in terms of the applications and the target platforms (e.g. increasing number of cores, more complex memory hierarchies), the Virtual Platform per se is not an answer to all of today’s design challenges. But by adding further abstraction to the models, an increasing need for automated mapping, refinement, and model transformations is needed. Formal, static, and dynamic analysis methods are increasingly dependent on platform details, requiring traceability during all design phases.

This workshop aims to bring together developers, researchers, and managers from industry and academia to develop a perspective for the future use of Virtual Platforms by exchanging knowledge about current and future requirements and their possible solutions. The workshop will also provide some space for the provision of state of the art and tangible results and session on tool demos.

 

Questions to be addressed during the workshop are:

  • How to efficiently generate a Virtual Platform for new applications and HW platforms?
  • How to close the implementation/refinement gap?
  • Which properties of a real system can be captured?
  • What are the requirements for future Virtual Platforms?
  • How can Virtual Platforms support the development of future real-time applications for MPSoCs?

In this workshop, different points of view will be discussed by

  • users of Virtual Platforms from different domains
  • tool vendors already offering Virtual Platform tools and modeling techniques, and
  • academic research institutes from around the world showing recent progress in Virtual Platform synthesis and core technologies.

More information can be found at: http://qvvp12.offis.de

23rd European SystemC User’s Group Meeting @ DATE 2011
Slides of presentation at ESCUG'23 (co-located with DATE'2011)
Philipp A. Hartmann, OFFIS

In many designs, a parametrisable number of modules, channels, ports, or other SystemC objects are used. Since such SystemC objects are usually named entities in the hierarchy, it is either required (in case of modules), or at least desired to pass a name parameter to the constructor of such objects. In this talk, an introduction to the convenience container called sc_vector<T> for collections of such objects is given, which will is part of the upcoming IEEE P1666-2011 SystemC standard to lift this burden.

  • «
  •  Start 
  •  Prev 
  •  1 
  •  2 
  •  Next 
  •  End 
  • »
Page 1 of 2

Newsflash

Successful final review meeting
On Thursday, May 25th, the final COMPLEX review meeting has been held in Brussels.

Read more...
 

Final public deliverables uploaded

All public COMPLEX deliverables are now available in the Deliverables section.

Read more...
 

COMPLEX @ ISCUG'2013 conference
14-15 April, 2013 - Noida, India

Read more...
 

Newsflash RSS Feed

COMPLEX News Feed