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NameD6.2.5 Final publishable summary report
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The consideration of an embedded device's power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this integrated project, integrated device manufacturers, system integrators, Electronic Design Automation (EDA) vendors and research partners collaboratively worked on solving the design challenges of today's heterogeneous HW/SW systems regarding power and complexity.

The main objective of the COMPLEX project was to increase the competitiveness of the European semiconductor, system integrator and EDA industry by addressing the problem of platform-based design space exploration (DSE) under consideration of power and performance constraints early in the design process. High performance usually causes high power consumption. A main challenge in today’s embedded system design is to find the perfect balance between performance and power. This balance cannot be found efficiently and at high quality, because until now no generic framework for accurately and jointly estimating performance and power consumption starting at the algorithmic level has been available.

As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies.

Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios.

FilenameCOMPLEX_D6.2.5_Final_publishable_summary_report.pdf
Filesize3.58 MB
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Created On: 05/10/2013 13:39
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