Home Project Description Work Packages WP 3: System exploration and optimization

WP 3: System exploration and optimization

This work package focuses on analysis and optimisation to support platform-based design space exploration under several standpoints. The baseline is to provide the designer with a proper system/application simulation and profiling environment to identify bottlenecks, statistics and metrics to be used throughout the system-level design exploration activities. In addition, a significant effort will be spent on the development of specific optimization strategies tailored for the hardware and software parts of the system architecture. Moreover, changing workloads and the status of the execution platform will be taken into ac­count by introducing ad-hoc run-time energy aware resource management strategies while fulfilling QoS constraints. The activities within the work package are clustered in the following five tasks.

T3.1 System simulation and profiling

The focus is the definition of a system-wide multi-level simulation and profiling strategy, including communica­tion for networked embedded systems, and the identification of metrics to support design space exploration. The virtual platform simulations from T2.2 and T2.5 will be enhanced with analysis and profiling tools so that a design space exploration loop becomes feasible (see WP2). Analysis and profiling metrics will be derived from T1.1.1 and T1.2, and will drive the performance optimizations for the system components in terms of the cost function defined in T1.2.3 (see WP1). The analysis information could be in the form of traces, and the abstraction for the simulation can range from the network level over SW task granularity to cycle accuracy. Tools will be developed that visualize the analysis results obtained from the simulations, and also an interchange format will be defined to pass analysis information from the virtual platform system to the exploration framework that will be developed in the other tasks of this work package.

T3.2 Embedded software optimisations

This tasks aims at optimizing the software side of the system at different abstraction levels. In addition to being the starting point for design space exploration and system-level optimization, energy and timing met­rics can be used for local and finer-grained optimizations. The goal is to identify directives to optimize tasks organization and OS/compiler usage, as well as to suggest source code transformations. At all abstraction levels, optimization takes the form of detailed and quantitative hints to the developer. Furthermore, thanks to the memory hierarchy modelling and memory access profiling, one of the envisaged output of the optimiza­tion phase is a dimensioning of the whole memory subsystem aimed at improving the efficiency of the appli­cation under analysis. The models developed in Task T2.2 (see WP2) and the data from design exploration (Task T3.4) will be adopted.

T3.3 Custom hardware optimisations

This task addresses the problem of introducing optimization techniques and code transformations into high-level synthesis design flows, together with hardware memory hierarchy optimisation. Different strategies can be used for optimising the design during behavioural synthesis, allowing a trade-off between power, per­formance and area. On a higher level of abstraction collected power and timing information can be used to identify power peaks and performance bottlenecks, allowing a trade-off between different implementations of the given algorithm/module. One focus will be on optimising memory traffic by replacing array structures in the SystemC code by register accesses. Other low-power high-level synthesis optimisations explored in this task are related to algorithmic transformations. The efficiency of different transformations will be evalu­ated and promising candidates are integrated into the high-level synthesis framework.

T3.4 Design-space exploration

The goal of this task is the definition of design space exploration methodologies for the optimisation of the target platform. This task will gain information from the platform analysis and simulation to efficiently tune the architectural parameters, the memory configuration and management and the HW/SW partitioning. Optimization is a multi-objective problem in terms of the system-level metrics. The required metrics for the DSE tool both of the initial, abstract model and the final, detailed, cycle-approximate model will be provided by a multi-level system simulation and performance analysis tool (developed in T3.1). In conjunction with such tool, a proper design space exploration framework for automatic tuning of the system platform configuration and IP selection will be developed, and a wide portfolio of models accounting for different memory configurations will be also considered.

T3.5 Run-time management

Assuming, that the system employs power management, either controlled by a dedicated HW unit or imple­mented in SW, this task optimizes the power and resource management policies which can be adopted at run-time, to fulfil also Quality of Service (QoS) constraints. The presence of a run-time manager (RTM) will facilitate the application development, by separating the application functionality from the underlying platform, while improving the efficient management of all platform resources especially when the operating context is dynamically chang­ing in terms of application requirements and physical constraints. A run-time resource manager at the operat­ing system level will be developed, tailored to optimize energy consumption under QoS constraints. Existing frameworks for power management together with the device/resource specific optimization strategies developed in WP3 will be taken into account. Development of a lightweight infrastructure to support run-time management of non-functional aspects will also be tack­led. This activity complements the more complex run-time management systems that are the main objective of this task, targeting very small hardware/software systems such as wireless sensor network nodes.

Last Updated ( Tuesday, 08 June 2010 14:49 )  

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