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COMPLEX @ DATE'2011 conference

COMPLEX @ DATE'2011 conference
14-18 March, 2011 - Grenoble, France

DATE'2011 logo

Introduction

The COMPLEX project is looking forward to present the current state of its progress to the European and international EDA community at the Design, Automation & Test in Europe (DATE'2011) conference.  A wide variety of activities of different project members at and around the DATE conference take place from 14-18 March, 2011 in Grenoble, France. Details about the overall conference programme, the exhibition, and the co-located workshops can be found on the conference website.


Project Booth at DATE Exhibition (Booth: EP16)

The DATE Exhibition is an excellent opportunity to meet and discuss the latest innovations in the EDA community alongside with the research-oriented conference itself.  The COMPLEX project will be present at the exhibition with a dedicated booth to give an overview of the achievements of the project's first year.  As a special highlight, a dedicated session in the Exhibition Theatre is scheduled as well.  Visit us at Booth EP16 to get in touch with the latest news on the design space exploration of complex systems, based on early estimation of power and timing combined to fast, augmented virtual platforms!

The main COMPLEX objectives are:

  • Highly efficient and productive design methodology and holistic framework for design space exploration of embedded HW/SW systems.
  • Combination and augmentation of well established ESL synthesis & analysis tools into a seamless design flow enabling performance & power aware virtual prototyping of the HW/SW system.
  • Interfacing next-generation model-driven SW design approach and industry standard model-based design environments.
  • Multi-objective co-exploration for assessing design quality and optimizing the system platform with respect to performance, power, and reliability metrics.
  • Fast simulation and assessment of the platform at ESL with up to bus-cycle accuracy at the earliest instant in the design cycle.
  • Optimization benefits from run-time mode adaptation techniques, such as dynamic power management or application adaptation to varying workloads.

If you're especially interested in a specific topic listed above, please let us know by sending a mail to complex-intern(at)offis.de.  We'd happily try to make a special appointment for a dedicated discussion at the COMPLEX Booth.

Additionally, two COMPLEX consortium members will be present at DATE's exhibition with dedicated booths:

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Early Timing and Power Information of Complex SoC Designs using Augmented Virtual Platforms

Exhibition Theatre, Thu, 17 March, 12:45 – 13:45

Rationale and Abstract

Consideration of an embedded system’s timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard and software as well as IP components. But prediction of the composed system behaviour can hardly be made.

In this session we present the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. They allow a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios.

Presentations:

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Friday Workshops

Several contributions have been prepared to different Friday workshops, traditionally co-located with DATE.

Workshop on Micro Power Management for Macro Systems on Chip (uPM2SoC'2011)

Poster

Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2011)

Poster

2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED'2011)

Talks

  • Towards SystemC Code Generation from UML/MARTE Concurrent System-Level Models. (14:15)
    Pablo Penil, Fernando Herrera and Eugenio Villar, UC.
  • Generation of Abstract IP/XACT Platform Descriptions from UML/MARTE for System-Level Performance Estimation. (14:30)
    Fernando Herrera and Eugenio Villar, UC.

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Last Updated ( Tuesday, 22 March 2011 13:22 )  

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