Home News COMPLEX @ DATE'2012 conference

COMPLEX @ DATE'2012 conference

COMPLEX @ DATE'2012 conference
12-16 March, 2012 - Dresden, Germany

Introduction

The COMPLEX project is looking forward to present the current state of its progress to the European and international EDA community at the Design, Automation & Test in Europe (DATE'2012) conference.  A wide variety of activities of different project members at and around the DATE conference take place from 12-16 March, 2012 in Dresden, Germany. Details about the overall conference programme, the exhibition, and the co-located workshops can be found on the conference website.


Project Booth at DATE Exhibition (Booth: EP8)

The DATE Exhibition is an excellent opportunity to meet and discuss the latest innovations in the EDA community alongside with the research-oriented conference itself.  The COMPLEX project will be present at the exhibition with a dedicated booth to give an overview of the achievements of the project's first two years.  Visit us at Booth EP8 to get in touch with the latest news on the design space exploration of complex systems, based on early estimation of power and timing combined to fast, augmented virtual platforms!

The main COMPLEX objectives are:

  • Highly efficient and productive design methodology and holistic framework for design space exploration of embedded HW/SW systems.
  • Combination and augmentation of well established ESL synthesis & analysis tools into a seamless design flow enabling performance & power aware virtual prototyping of the HW/SW system.
  • Interfacing next-generation model-driven SW design approach and industry standard model-based design environments.
  • Multi-objective co-exploration for assessing design quality and optimizing the system platform with respect to performance, power, and reliability metrics.
  • Fast simulation and assessment of the platform at ESL with up to bus-cycle accuracy at the earliest instant in the design cycle.
  • Optimization benefits from run-time mode adaptation techniques, such as dynamic power management or application adaptation to varying workloads.

If you're especially interested in a specific topic listed above, please let us know by sending a mail to complex-intern(at)offis.de.  We'd happily try to make a special appointment for a dedicated discussion at the COMPLEX Booth.

SWAT demonstration session

On Thursday, 10:00-12:00, an on-site demonstration of the Software Analysis Toolset (SWAT) will be given at the COMPLEX booth.  More details on SWAT can be found in the tool flyer.

back to top


Publications

Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization

Haroon Mahmood, Massimo Poncino, Enrico Macii, Politecnico di Torino, IT
Mirko Loghi, University di Udine, IT

Abstract

Power management of caches based on turning idle cache lines into a low-energy state is also beneficial for the aging effects caused by Negative Bias Temperature Instability (NBTI), provided that idleness is correctly exploited; unlike energy, aging, being a measure of delay, is in fact a worst-case metric. In this work we propose an application-specific partitioned cache architecture in which a cache is organized as a set of independently addressable sub-blocks; by properly using the idleness of the various banks to drive how the partition is determined, it is possible to extend the effective lifetime of the cache while saving extra energy.

Two are the distinctive features of our approach: First, we allow the cache sub-blocks age at different rates, achieving a sort of graceful degradation of performance while extending lifetime beyond the limits of previously published works. Proper architectural arrangements are also introduced in order to cope with the issue of using a progressively smaller cache. Second, the sub-blocks have non-uniform sizes, so to maximally exploit idleness for joint energy and aging optimization.

Simulation results show that it is possible to extend the effective lifetime of the cache by more than 2x with respect to previous methods, while concurrently improving energy consumption by about 50%.

The COMPLEX Eclipse Framework for UML/MARTE Specification of Embedded Systems and
Automatic Generation of Executable Models for Design Space Exploration

F Herrera, P Peñil and E Villar, U Cantabria, ES
F Ferrero and R Valencia, GMV Aerospace and Defence SAU, ES

  • University Booth demonstration
  • Tuesday      (Session 2; 12:30 - 14:30, P09)
  • Wednesday (Session 5, 10:00 - 12:30, P04)
  • Thursday     (Session 9, 10:00 - 12:30, P04)
  • Booth 50, Exhibition

Abstract

The high complexity and variety of applications and platforms in current embedded systems is tackled by ESL design methodologies by means of several advanced concepts and languages. In the first and critical system specification step, the adoption of the Model Driven Engineering (MDE) principles make possible to raise the abstraction level in the development process and take advantage of automation capabilities to generate implementation code and analysis models. Moreover, the UML language and the recent MARTE profile enable a standardized way for describing the system. The standard SystemC language, Transaction Level Modeling (TLM), and modern performance analysis techniques, such as native simulation or virtualization, have enabled the building of fast executable models for functional validation and performance analysis. Fast performance analysis models are crucial for tackling the design space exploration (DSE) activity, in order to do early right decisions from a wide design space. This demo booth will present the COMPLEX Eclipse-based UML/MARTE ESL design framework, developed by the Microelectronics Engineering Group of the U Cantabria (GIM/UC) jointly with GMV in the COMPLEX FP7 project.

This framework integrates the aforementioned design principles, and provides innovative enhancements, such as separation of concerns and the description of the design space embedded in the architectural description of the system. Specifically, the demo booth will focus on the UML/MARTE modelling, using an Enhanced Full Rate (EFR) vocoder fully compliant with the GSM standard as example, and on the automated generation of the executable performance model for functional validation and for fast performance analysis. First, the demo will show how the whole EFR Vocoder is specified, including its functionality, split into components, and how the architecture of the application is described. The demo will also highlight how the SW/HW platform is described, and the architectural mapping (i.e. allocation of the application components to the platform resources). Special remark will be put on the presentation of the capability of the specification methodology for the definition of the design exploration space. That is, the model built actually represents several implementation solutions, defined through the use of design parameters (e.g., frequencies, number of cores, etc), rules and constraints that define a set of architectural solutions that define the design exploration space. It will be also shown how to specify the output metrics to be analysed, such as power consumption and application latencies. In a second part, the demo will demonstrate how the executable performance model is simply and automatically generated through the Eclipse-based environment. Additionally, it will highlight the insights on how this automation level is achieved through a set of model-to-text generators, and the mechanisms that permit the framework to be customized with new analysis and transformation engines. The attendee will also see the generated executable model, its fast simulation, and how the simulation enables a bit accurate functional validation . Moreover, the performance output data, and the output formats, which make this framework especially suited for DSE, will be shown.

back to top


Friday Workshops

Several contributions have been prepared to different Friday workshops, traditionally co-located with DATE.

Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow (QVVP'2012)

Presentation

Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2012)

Poster

  • Energy-aware run-time management in video surveillance systems
    Laurent San (Thales), Sara Bocchio (ST-I), Chantal Ykman-Couvreur (IMEC), Gianluca Palermo (PoliMi), Philipp A. Hartmann (OFFIS)

back to top

Last Updated ( Monday, 16 July 2012 09:25 )  

Newsflash

Successful final review meeting
On Thursday, May 25th, the final COMPLEX review meeting has been held in Brussels.

Read more...
 

Final public deliverables uploaded

All public COMPLEX deliverables are now available in the Deliverables section.

Read more...
 

COMPLEX @ ISCUG'2013 conference
14-15 April, 2013 - Noida, India

Read more...
 

Newsflash RSS Feed

COMPLEX News Feed