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COMPLEX @ CODES+ISSS'2012

COMPLEX @ CODES+ISSS'2012
07-12 October 2012 - Tampere, Finland
special session (slides available)

 

COMPLEX @ CODES+ISSS'2012 conferenceCODES ISSS

The COMPLEX project has been present at the CODES+ISSS'2012 conference, which was held in conjunction with the Embedded Systems Week (ESWeek) from 07-12 October 2012 in Tampere, Finland. The International Conference on Hardware/Software Codesign and System Synthesis is the premier event in design, modeling, analysis, and implementation of modern embedded systems, from system-level analysis and optimization to hardware/software implementation. The conference covers range of design problems and applications relevant to important embedded system quality metrics including performance, cost, power consumption, reliability, security, usability, and compactness.  As such, it is the perfect venue to present the latest results of the COMPLEX project in terms of a special session.

COMPLEX special session

Synthesis of Executable Extra-Functional System-Level Models for Timing and Power Exploration

Date: Wednesday, October 9, 1300-1500
Room: Sonaatti 2 (Session 8B)

Abstract

In the design of embedded systems extra-functional properties like time and power need to be considered during the entire design process. Often these properties can only be estimated after manually implementing a design for a certain target platform and using state-of-the-art timing and power analysis tools. This special session aims to present current research towards automatic synthesis of executable system-level timing and power models for early exploration. The different papers cover model-driven design, performance model synthesis, and model-driven design-space exploration of embedded software, synthesis of dynamic power management for embedded software on low-power CPUs, RTL to TLM re-synthesis and abstraction of timing and power properties, run-time resource management for heterogeneous MPSoCs obtained from system-level extra-functional models, and power-aware configuration and synthesis of networked embedded applications.

Papers

Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero and Raúl Valencia. An MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'2012). Tampere, Finland, October 2012. [bib]

@inproceedings{codes2012:211i,
	author = "Herrera, Fernando and Posadas, Hector and Peñil, Pablo and Villar, Eugenio and Ferrero, Francisco and Valencia, Raúl",
	title = "An MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models",
	booktitle = "International Conference on Hardware/Software Codesign and System Synthesis",
	series = "CODES+ISSS'2012",
	year = 2012,
	month = "October",
	location = "Tampere, Finland",
	numpages = 10
}

Carlo Brandolese and William Fornaciari. Software Energy Optimization Through Fine-Grained Function-Level Voltage and Frequency Scaling. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'2012). Tampere, Finland, October 2012. [bib]

@inproceedings{codes2012:212i,
	author = "Brandolese, Carlo and Fornaciari, William",
	title = "{Software Energy Optimization Through Fine-Grained Function-Level Voltage and Frequency Scaling}",
	booktitle = "International Conference on Hardware/Software Codesign and System Synthesis",
	series = "CODES+ISSS'2012",
	year = 2012,
	month = "October",
	location = "Tampere, Finland",
	numpages = 8
}

Daniel Lorenz, Kim Grüttner, Nicola Bombieri, Valerio Guarnieri and Sara Boccio. From RTL IP to Functional System-Level Models with Extra-Functional Properties. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'2012). Tampere, Finland, October 2012. [bib]

@inproceedings{codes2012:213i,
	author = "Lorenz, Daniel and Grüttner, Kim and Bombieri, Nicola and Guarnieri, Valerio and Boccio, Sara",
	title = "{From RTL IP to Functional System-Level Models with Extra-Functional Properties}",
	booktitle = "International Conference on Hardware/Software Codesign and System Synthesis",
	series = "CODES+ISSS'2012",
	year = 2012,
	month = "October",
	location = "Tampere, Finland",
	numpages = 10
}

Chantal Ykman-Couvreur, Philipp A Hartmann, Gianluca Palermo, Fabien Colas-Bigey and Laurent San. Run-time Resource Management based on Design Space Exploration. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'2012). Tampere, Finland, October 2012. [bib]

@inproceedings{codes2012:214i,
	author = "Ykman-Couvreur, Chantal and Hartmann, Philipp A. and Palermo, Gianluca and Colas-Bigey, Fabien and San, Laurent",
	title = "Run-time Resource Management based on Design Space Exploration",
	booktitle = "International Conference on Hardware/Software Codesign and System Synthesis",
	series = "CODES+ISSS'2012",
	year = 2012,
	month = "October",
	location = "Tampere, Finland",
	numpages = 9
}

Parinaz Sayyah, Mihai Lazarescu, Davide Quaglia, Emad Ebeid, Sara Bocchio and Alberto Rosti. Network-aware Design-Space Exploration of a Power-Efficient Embedded Application. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'2012). Tampere, Finland, October 2012. [bib]

@inproceedings{codes2012:215i,
	author = "Sayyah, Parinaz and Lazarescu, Mihai and Quaglia, Davide and Ebeid, Emad and Bocchio, Sara and Rosti, Alberto",
	title = "{Network-aware Design-Space Exploration of a Power-Efficient Embedded Application}",
	booktitle = "International Conference on Hardware/Software Codesign and System Synthesis",
	series = "CODES+ISSS'2012",
	year = 2012,
	month = "October",
	location = "Tampere, Finland",
	numpages = 8
}

Program

  • Welcome and Introduction (slides)
    Kim Grüttner (OFFIS, Germany)
  • An MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models (slides)
    Eugenio Villar (University of Cantabria, Spain)

Abstract: This talk presents the COMPLEX UML/MARTE modeling methodology and its related framework for automatic generation of executable performance models. The modeling methodology supports Model Driven Development (MDD), required by industrial flows, and a novel set of modeling features specifically suited for Design Space Exploration (DSE), a crucial design activity. The COMPLEX framework presents other main advantages for DSE. The COMPLEX tooling enables the automatic generation of an executable and configurable model for fast performance analysis without requiring engineering effort. The COMPLEX tooling automates the production of an easily portable text based representation of the UML/MARTE model. This text-based representation is read by the underlying simulation infrastructure, which automatically builds a fast performance model supporting the evaluation of different configurations of the system. A main aspect of the performance analysis framework is that it supports a system-level text-based front-end, which it is produced from the COMPLEX UML/MARTE model, and which avoids the development of SW implementations, HW refinements, or the implementation of HW/SW interfaces. Moreover, neither code regeneration, nor recompilation is required for all the DSE iterations, and thus, the time of the exploration is mostly due to model simulation.

  • Energy and timing analysis and optimization of embedded applications (slides)
    William Fornaciari, Carlo Brandolese (Politecnico di Milano, Italy)

Abstract: This talk presents a methodology and a toolchain to perform estimation and optimization of the energy consumption associated to software execution on tiny embedded systems. The estimation phase is based on an ISA-level characterization of the target processor, while the optimization phase is made combining the estimation process with design space exploration in order to exploit fine-grained dynamic voltage and frequency scaling. The proposed approach operates at compile-time, with the granularity of single C functions and almost automatically augments the source code.

  • From RTL IP to functional system-level models with extra-functional properties (slides)
    Daniel Lorenz (OFFIS, Germany)

Abstract: The talks presents a novel abstraction methodology for generating time- and power-annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration. With the proposed approach, IP models can be natively integrated into SystemC TLM-2.0 platforms and executed 10-1000 times faster compared to state-of-the-art RTL simulators. The abstraction methodology guarantees preservation of the behaviour and timing of the RTL models. Target technology dependent power properties of IP components are represented as power state-machines and integrated into the abstracted TLM models. The experimental results show a relative error less than 10% of the abstracted model's power consumption compared to state-of-the-art RTL power simulators. The evaluation has been performed on RTL IP components with different characteristics and demonstrates the effectiveness of the presented abstraction methodology.

  • Run-time resource management based on design space exploration (slides)
    Chantal Couvreur (IMEC, Belgium)

Abstract: A main challenge in today's embedded system design is to find the perfect balance between performance and power consumption.  This paper presents a run-time resource management framework for embedded heterogeneous multi-core platforms. It allows dynamic adaptation to changing application context and transparent optimization of the platform resource usage following a distributed and hierarchical approach. A Global Resource Manager (GRM) is running in parallel with the central manager of the application on the host processor of the platform. Each IP core of the platform can execute its own Local Resource Manager (LRM), and the GRM conforms to practices of each LRM. The operating points managed by the GRM are identified in a design-space exploration phase as a set of Pareto-optimal configurations of the application and their impacts with regards to the quality of experience, performance and energy consumption. The GRM has already been integrated in a POSIX version of an audio-driven video surveillance application in order to maximize its QoE parameters with respect to the battery duration and the energy budget of the platform, used to analyze the GRM efficiency.

  • Network-aware Design-Space Exploration of a Power-Efficient Embedded Application (slides)
    Parinaz Sayyah (Politecnico di Torino, Italy)

The talk presents the design and multi-parameter optimization of a networked embedded application for the health-care domain. Several hardware, software, and application parameters, such as clock frequency, sensor sampling rate, data packet rate, are tuned at design- and run-time according to application specifications and operating conditions to optimize hardware requirements, packet loss, power consumption.  Experimental results show that further power efficiency can be achieved by considering also communication aspects during design space exploration.

  • Panel discussion
    (all speakers)
Last Updated ( Tuesday, 16 October 2012 20:39 )  

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