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Concept and Motivation

The main objective of the COMPLEX project is to increase the competitiveness of the European semiconductor, system integrator and EDA industry by addressing the problem of platform-based design space exploration (DSE) under consideration of power and performance constraints early in the design process. High performance usually causes high power consumption. A main challenge in today’s embedded system design is to find the perfect balance between performance and power. This balance can not be found efficiently and at high quality, because until now no generic framework for accurately and jointly estimating performance and power consumption starting at the algorithmic level is available. This can only be achieved in cooperation on a European level, taking into account European platform providers, system developers/integrators, EDA companies, Universities and research institutes from both, the HW and the embedded SW world.

The COMPLEX project will enable the European semiconductor and electronic system industry to achieve a break through in product quality through substantially improved performance and power efficiency. This quantum leap will be achieved by a new design environment for platform-based design-space exploration offering developers of next-generation mobile and embedded systems a highly efficient and productive design methodology and tool chain allowing them to iteratively explore and refine their applications to meet market requirements. The design technology in particular enables the fast simulation and assessment of the platform at Electronic System Level (ESL) with up to cycle accuracy at the earliest instant in the design process. Several new modelling, exploration and simulation concepts will be developed and combined with well established ESL synthesis, cross-compilation, analysis and simulation tools into a seamless holistic design flow enabling performance & power aware virtual prototyping from a combined hardware-software perspective.

High performance usually causes high power consumption. Especially in embedded system design today one main objective is to find the perfect balance between performance and power for a given design. One strategy is to optimise the performance everywhere where speed is absolutely needed and to design everything else for low power. This helps to achieve the ultimate goal of handheld embedded devices, ensuring the required performance with the longest possible battery life.

Figure 1 shows the key challenges for the embedded mobile device industry. The performance growth of mobile phones per generation from analogue (1G) over GSM (2G) to high bandwidth (3G and 4G), clearly exceeds Moore’s law of technology development. Instead it follows the much faster Shannon’s law of application development, predicting a complexity doubling in 8.5 month. Since more than 30 years now the integration density of integrated circuits approximately doubles every 18 months (Moore’s Law). In contrast, battery makers need 5 to 10 years to achieve comparable increase in power density, and memory access time performance doubles every 12 years only.

Figure 1: Key Technology Gaps

The gaps in this figure define the challenges which the industry is facing: 1. Algorithmic complexity gap, 2. Microprocessor and memory bandwidth gap, and 3. Power reduction gap.

In order to keep up with the rapid technological advances, system design methodologies and EDA support were always forced to evolve in the past. Without the support of design methodologies and appropriate tool support the design gaps are becoming larger. In the COMPLEX project we address all three gaps

  • We observe a rising complexity of applications and execution platforms. The gap between these complexities boosts the uncertainty of platform selection and application to platform mapping, and requires EDA tools and methods that are fast enough to cope with the very size of recent algorithms.

  • Since the power reduction gap is the next main limiting factor, a balance between performance and power needs to be found early in the design process. This can only be performed under explicit consideration of the application. To ensure a sufficient power control, tools and methods have to be not only fast enough, but also accurate in prediction and efficient in optimization.
  • The gap of memory access times requires smarter memory organization. Since this influences both power and performance a multi-objective design space exploration is required.

In custom hardware design, advances in performance and power consumption have been mainly influenced by new technologies and an evolution in design methodology. The latter was achieved by several important steps in climbing up the level of abstraction for the design entry. All these steps gave the productivity in hardware design a great boost and made it possible to manage the steadily growing complexity of integrated circuits. Software processing units like microcontrollers, SIMD processors or DSPs have been made more efficient. Modern plat­forms support advanced power management capabilities with dynamic frequency scaling (sometimes independent for processing and memory subsystem) and power islands that needs to be effectively controlled to maximise the optimization potential.

For these reasons it is high time to initiate the next ground-breaking step in addressing the formulated challenges in a holistic approach. Thus, there is a need for a new evolving design entry at system level where hardware and software are described in the same way. The latest trends in software engineering and hardware design have some commonalities which might be not apparent on the first look. In the hardware and software world we observe the introduction of methodologies that separate the functionality/algorithm from the concrete implementation platform. The HW world calls this evolution ESL; the SW world calls this model-based design or MDE (Model-Driven Engineering), with Model-Driven Architecture (MDA). Both follow the Y-chart approach (separation of functionality – what – from the implementation platform – how).

The availability of this new design entry in conjunction with the traditional bottom-up approach defines a new viewpoint for the design of embedded systems: How to find a mapping and implementation of an application onto an execution platform that fulfils all functional and non-functional requirements at minimal cost. To avoid expensive redesigns and costly code modifications, the platform decision should be done before investing money into a concrete target platform. For this purpose reliable information about the execution behaviour of the application running on the platform in terms of functionality, performance and power consumption are absolutely mandatory.

Until now no generic framework for accurately and jointly estimating performance and power consumption of complete embedded systems is available at the algorithmic level. This can only be achieved in cooperation on a European level, taking into account different players: European platform providers, system integrators, EDA companies, Universities and research institutes from both, the HW and the embedded SW world.

Available point-tools and predesigned system components need to be bundled and properly integrated into a holistic framework for platform-based design space exploration:

  • Behavioural synthesis for the generation of custom hardware from algorithmic descriptions
  • Dedicated embedded SW compilers for the generation of executables from algorithmic descriptions
  • Portfolio of HW intellectual property, ranging from microprocessors, DSPs, memories, on-chip communication structures, communication peripherals, and domain specific accelerators.
  • Virtual platforms for early system simulation, analysis and integration of HW and SW components without using costly test-chips.

The motivation of COMPLEX is to build a framework on top of these assets that supports a software-like design entry, integrates platforms and software development tool-chains from different European providers, and incorporates European EDA tools and know-how in the area of power and timing estimation of HW, SW and run-time power management. The project outcome is the connection of this framework to the next-generation system specification and design methodology, the automatic generation of an efficient executable virtual system, giving accurate and reliable timing and power information, and the integration of an automatic design space exploration for finding the optimal design space instance parameters.

Last Updated ( Thursday, 27 May 2010 18:15 )  

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Successful final review meeting
On Thursday, May 25th, the final COMPLEX review meeting has been held in Brussels.

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Final public deliverables uploaded

All public COMPLEX deliverables are now available in the Deliverables section.

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COMPLEX @ ISCUG'2013 conference
14-15 April, 2013 - Noida, India

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