WP 2: Estimation and model generation

The main goal of WP2 is the development of the multi-level, virtual system executable model able to provide the performance figures required for Design-Space Exploration (DSE) in WP3.

The starting point will be the system specification in UML/MARTE and Matlab/Stateflow. From these specification means, the initial, system-level executable model in SystemC and the initial IP-XACT archi­tecture will be generated. As shown in the Figure below, two abstraction levels are considered. The first one corresponds to the system model before architectural mapping. At that stage, the main design objective is to decide the system architecture in terms of number and kind of platform resources to be used, the mem­ory architecture, the interconnection architecture, the custom IP components to integrate and the allocation of the system functions to specific platform resources, i.e. processors and custom HW. After architectural map­ping, a more detail, TLM (Transaction-Level Modelling) model can be used for architectural optimization.

In order to support this multi-level performance analysis, performance models will be developed able to es­timate the main quality figures of the system components (i.e. execution times, complexity, power consump­tion, etc.) at both system-level as well as TLM. These performance models will provide the performance characteristics of the whole system when simulating the complete virtual system model.

COMPLEX virtual platform generation overview

At system-level, a fast, sufficiently accurate analysis of the component’s performance if mapped on a specific platform resource will be done. Based on this high-level system profiling, the concrete metrics required for system-level Design-Space Exploration (DSE) will be generated. More accurate, slower models will be ap­plied after architectural mapping, once the concrete allocation and extraction of each function on a concrete platform resource using concrete communication mechanisms has been performed.

The work is structured in the following Tasks:

T2.1 Model-driven design front-end

In this task, the initial, system-level, executable SystemC specification will be generated from the functional specification means provided to the system engineer, Matlab/Stateflow and UML/MARTE. With these two formalisms, a wide range of embedded systems is covered. This initial system architecture will be optimized during the DSE process.

T2.2 Embedded Software

In this task, performance and power estimation of embedded software is performed. This includes current state-of-the-art techniques, like cross-compilation for the specific target processor and source-code analysis. Based on these pre-processing steps the estimation of power and performance (i.e. execution time) at system and TLM levels is done.

T2.3 Platform IP components

In this task, the definition and implementation/integration of platform IP component models for memories, communication resources (buses, point-to-point connections, or networks-on-chip), and dedicated hardware accelerators is performed.

T2.4 Custom hardware

This task is the counterpart of T2.2; performance and power estimation of custom hardware is performed. For the hardware estimation and simulation model generation, the same levels of abstraction as for the em­bedded software in T2.2 are considered.

T2.5 Virtual system generation

This task combines the results from T2.2, T2.3, and T2.4 into an executable, multi-level, self-simulating system description, predicting the system behaviour under the use-case defined workload models with up-to cycle and/or instruction accuracy. A Virtual System Generator will be developed able to read the timing and power instrumented C/C++ code for SW and user-defined HW components, which is the output of the tools developed in T2.2 and T2.4. From T2.3 it obtains virtual component implementations of memories, intercon­nection and pre-designed dedicated HW components. The result will be a unified simulation and perform­ance analysis framework.

 

Last Updated ( Tuesday, 08 June 2010 14:47 )  

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