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HIFSuite/A2T

HIFSuite is a set of tools and file formats for Automatic HDL Conversion and Abstraction. This means that with HIFSuite you can translate RTL modules from VHDL or Verilog to SystemC 2.0, either RTL or TLM. If the conversion into TLM is chosen it is called abstraction.

The tools are C++ applications that can be run and configured directly from the command line and they are available both for Linux and for Windows.

The following figure shows the diagram of the elaboration flow, starting from the original RTL module modeled with VHDL or Verilog, ending with the converted SystemC module. In the middle is the HIF Format used to create a local representation of the design independent from the original description language. At this stage the module can be manipulated using the Core API and then converted into SystemC. This manipulation strategy is used by the Automatic Abstraction Tool and by the Hierarchy Remover tool to create the TLM counterpart of a design and it can be used by designers to create custom manipulation tools.


 

Figure 1: HIFSuite conversion and abstraction flow.

The Parsing tools are used to build the internal representation of the original module (Front-End), while the Generator tools are used to create final version of the module (Back-End). At least One Parser or one Generator for each language supported by HIFSuite must exist.

The A2T is responsible to apply the transformation to the design according to the SystemC TLM 2.0 specifications.The Hierarchy Remover is a utility tool that allows to flatten the hierarchy in the design. It is useful to remove the module's internal hierarchy when only the interfaces are relevant in the final design. This is the case of the abstraction, which is used to get a new module that is equivalent in terms of behavior and not in terms of structure.

Once the original module is imported and converted into its equivalent HIF representation, the designer may apply any kind of change and transformation using the Core API. The Core API is a set of C++ functions that work on the internal representation of the module. . The HIF (HIF stands for Heterogeneous Interchange Format) is a structured format suitable to represent hierarchical designs. It can be dumped to file as XML when a readable format is required.

The process that abstracts an RTL description towards a TLM description relies on a formal model that allows us to represent designs at different abstraction levels. Among different alternatives, we select the extended finite state machine (EFSM). Given an EFSM of the RTL IP, the proposed abstraction technique is composed of the following main steps:

  1. Identification of computational phases. An EFSM can be subdivided in three different kinds of subgraphs composing the behavior of the RTL IP. They are: input subgraphs, where the IP gets data from the primary inputs, elaboration subgraphs, where the IP computation is carried out, and output subgraphs, where the computation result is put to the primary outputs. Paths inside such subgraphs represent different computational phases of the design. Subgraphs and computational phases are identified and used in the subsequent steps of the methodology for generating the TLM functionality and communication interface.
  2. Generation of the TLM functionality. States composing each elaboration subgraph are merged into a single macro state. We obtain a macro state per elaboration subgraph by applying appropriate merging rules.
  3. Generation of the TLM communication protocol. The communication protocol of the TLM IP is generated by implementing an interface compliant with the OSCI TLM-2.0 standard library, to guarantee the generated model interoperability and reuse. Moreover, an opportune TLM IP driver is implemented to allow the master to correctly interface to the TLM IP. The communication protocol and the driver are automatically implemented by analyzing the input and output subgraphs of the RTL EFSM.
Last Updated ( Saturday, 18 May 2013 21:52 )  

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