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PowerOpt is an existing high-level synthesis and power estimation tool. It accepts a design specification in C, C++, or SystemC as input and produces a power optimized Verilog/VHDL description. During the COMPLEX project, PowerOpt was extended by functionality generate for generating a block annotated C++ specification (BAC++) for custom hardware components of a design. The BAC++ is a cycle-accurate description of the behaviour augmented with power and timing information. It allows the annotation of extra functional properties of the synthesised component at basic block granularity. A detailed description of the generated code is given in D2.4.2. Along with the executable BAC++ model an XML-based power mode table is generated, containing all supported power modes and average power values based on the combination of supply voltage and clock frequency the design had been characterised for. The power modes are required for simulation as well as for the configuration of a global resource manager (GRM).

The new functionality is based on the existing PowerOpt functionality that internally creates a control data flow graph (CDFG), performs a high level synthesis, and generates a power and timing characterised RT-level data path and its controller’s FSM. The internal representation of the generated FSM and the RT-level data path are used to identify and characterize the hardware basic blocks. From the HBBs, augmented BAC++ code is generated. Figure 1 gives an overview on the basic tool flow.

Figure 1: Existing and extended basic PowerOpt tool flow

Next to the BAC++ executable model, information about the identified hardware basic blocks (HBBs) is generated as part of the extended functionality. This information includes statistical data on the identified HBBs, covering their size in terms of number of RT components and their power consumption. This statistical data is written to a file in the CSV format. Furthermore, a graph representation of the HBBs is written to a file in DOT format. This file can be used to create various graphical representations using the Graphviz tool suite. It is also worth mentioning that the generated BAC++ code relies on functionality that has been implemented in a library, also as part of the COMPLEX project.

The new functionality that analyses the internal controller and data path representation, identifies the hardware basic blocks, and generates the augmented C++ model, as well as the additional output files, has been made accessible by a single new tool command. The command is called analyse_hbb and provides several options to control the generation of the desired output files. This new command is to be executed after conventional synthesis and power estimation had been performed in order to have all required information available.

Last Updated ( Saturday, 18 May 2013 22:52 )  


Successful final review meeting
On Thursday, May 25th, the final COMPLEX review meeting has been held in Brussels.


Final public deliverables uploaded

All public COMPLEX deliverables are now available in the Deliverables section.


COMPLEX @ ISCUG'2013 conference
14-15 April, 2013 - Noida, India


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