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Synopsys VP

The Synopsys Virtual Platform simulator in the context of the COMPLEX project refers to 2 variants of the same simulation environment.

A first variant of the virtual platform simulator is used in Use Case 3. In this case the virtual platform simulator is used as a reference platform to validate the design decisions taken in the design space exploration loop. The platform is the result of the UML/MARTE to IP-XACT design flow. In this case the platform is automatically generated from the UML/MARTE description via the IP/XACT XML intermediate format. The virtual platform performance models are used in the simulator for the design validation step. For this flow the existing Virtual platform tool-suite is reused and has been integrated into the overall COMPLEX design flow. The virtual platform that is delivered is depicted in the picture below. The virtual platform comes with a SW development and validation environment so that the application mapping and functionality can be validated and if necessary also debugging is possible.


The second variant of the virtual platform simulation environment is used in Use Case 2. Here the virtual platform simulator is extended with a task modelling library and abstract architecture modelling environment. Furthermore the virtual platform creation framework is extended to support application mapping and support for design space exploration. Additionally extensions for constraint modelling as well as support for power modelling have been added.

To support embedded software estimation the virtual platform simulation environment is extended with a modelling framework that supports application modelling and abstract architecture modelling. Application modelling is supported through the creation of a task modelling API and a generic task library. Using the task library basic function estimators can be assembled together into a full application model. In order to perform embedded software estimation the application model needs to be complemented with an architecture model. The architecture model consists out of Virtual Processing units that are configurable to represent different processing architectures. By mapping the application model to the architecture the relationship between function estimators and processing units can be established. This combination results in a system estimator for embedded software, the different processing modes of the application can now be configured and performance and power estimations can be obtained from the simulator. A more detailed description of the extensions to the virtual platform simulation solution can be found in D2.2.2 “Final report on embedded software estimation and model generation”.

 

Last Updated ( Saturday, 18 May 2013 22:51 )  

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